1. Field
Embodiments described herein generally relate to methods and apparatuses for forming semiconductor devices. More particularly, embodiments described herein generally relate to methods and apparatuses for manufacturing an interconnect structure for semiconductor devices utilizing a selective protection process during a pattering process.
2. Description of the Related Art
Reliably producing nanometer and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI interconnect technology have placed additional demands on processing capabilities. Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
As the dimensions of the integrated circuit components are reduced (e.g., to nanometer dimensions), the materials used to fabricate such components must be carefully selected in order to obtain satisfactory levels of electrical performance. For example, when the distance between adjacent metal interconnects and/or the thickness of the dielectric bulk insulating material that isolates interconnects have nanometer dimensions, the potential for capacitive coupling between the metal interconnects is high. Capacitive coupling between adjacent metal interconnects may cause cross talk and/or resistance-capacitance (RC) delay which degrades the overall performance of the integrated circuit and may render the circuit inoperable. In order to minimize capacitive coupling between adjacent metal interconnects, low dielectric constant bulk insulating materials (e.g., dielectric constants less than about 4.0) are needed. Examples of low dielectric constant bulk insulating materials include silicon dioxide (SiO2), silicate glass, fluorosilicate glass (FSG), and carbon doped silicon oxide (SiOC), among others.
A patterned mask, such as a photoresist layer or a hard mask layer, is commonly used to etch structures, such as gate structures, shallow trench isolation (STI), bit lines and the like, or back end dual damascene structures on a substrate. The patterned mask is conventionally fabricated by using a lithographic process to optically transfer a pattern having the desired critical dimensions to a layer of photoresist. The photoresist layer is then developed to remove undesired portions of the photoresist, thereby creating openings in the remaining photoresist.
However, the patterned mask, which is typically formed on an upper surface of the structure to be etched, often contribute an increase of the trench/via aspect ratio, which creates challenge for the metal gap filling process. As such, it is often desired to remove the patterned mask from the substrate prior to the metallization process so as to lower the aspect ratio of the vias/trenches to facilitate metal filling into the vias/trenches during the metallization process. Conventionally, dry etching or wet etching process can both be utilized to remove the patterned mask. However, conventional processes often adversely damage sidewalls or features in the interconnect structure, resulting in line collapse or profile deformation.
Damage caused to the structure may result in inaccurate critical dimension of the feature formed on the substrate may result in poor electrical properties of the device. Poor electrical properties of the device may impact not only the electrical performance of the devices, but also on the integration of the interconnection structure, including insulating materials and conductive materials, which may eventually lead to device failure.
Thus, there is a need for improved methods to selectively control and protect certain areas of the structures on a substrate from damage during a patterned mask removal process.